1. Field of the Invention
This invention relates to a method, and the resulting structure, of fabricating semiconductor devices, and more specifically to a method of fabricating a multilevel planarized interconnection metallurgy system for integrated circuit devices.
2. Description of the Prior Art
The feature size in the state of the art of very large scale integrated circuits (VLSIs) such as high density memory chips, microprocessors and the like, has shrunk to the submicron level.
As the metal lines of the interconnection metallurgy systems have decreased, it is important to maintain as great a degree of surface planarity as possible. Surface planarity is critical in order (1) to accommodate the very shallow depths of fields of optical apparatus used for exposing the resist layers necessary to produce the metallurgy patterns, (2) to maintain a uniform metallurgy stripe thickness and (3) to avoid metal stringers.
When the initial metallurgy stripe pattern is formed on the planar surface of a substrate, it is subsequently covered by a dielectric layer. If the layer is conformal in nature, the resulting dielectric surface will be non-planar, i. e. the surface of the dielectric layer will dip down between the metal strips and thus present a surface with different levels. When a plurality of metallurgy layers are deposited, and each covered with a dielectric layer, each successive layers will contribute to the non-planarity, since there may be areas where a plurality of metal stripes are aligned or overlapped, and other areas where there may be less or no overlapped stripes.
A great deal of progress has been made in depositing the dielectric layer, so that the areas between the stripes will be filled while maintaining a greater degree of planarity. Such techniques include spin-on-glass (SOG) techniques, atmospheric pressure chemical vapor deposition (APCVD) techniques, tetraethylorthsilicate deposition in an atmosphere that contains O.sub.3 (TEOS/O.sub.3), and the like. These techniques have the capability to completely fill and locally planarize submicron gaps. These deposition techniques may be followed by an etch back to further promote planarity. The techniques are explained in an article in January 1992 Microelectronics Manufacturing Technology, Pages 22-27, entitled "Improved Sub-Micron Inter-Metal Dielectric Gap Filling using TEOS/Ozone APCVD".
However, while the above techniques fill submicron gaps between closely spaced metal lines, they are generally incapable of filling gaps between more distantly spaced lines. The problem is more clearly illustrated in FIGS. 1-5. FIGS. 1-5 show a semiconductor substrate 10 having a field effect transistor including source and drain regions 12, and gate 14. The substrate 10 also has a field oxide layer 16, and a relatively thick borophosphosilicate glass (BPSG) layer 18. A first metallurgy level including closely spaced metal stripes 20, and a widely spaced stripe 22, are shown in cross section. This is a typical device cross section, which illustrates the planarity problem presented by non-uniformly spaced metal stripes.
The reason for the non-uniform spacing is that the interconnection system must join the devices in an operative circuit, and it is not possible to design such a circuit where all the lines are uniformly spaced and parallel. In FIG. 2, there is illustrated the deposition of environment. FIG. 3 shows a dielectric layer 26 deposited by spin-on-glass techniques. Note that the gaps between closely spaced metal lines 20 are filled, but the wide gap between lines 20 and 22 is not filled, because of the limitations of the prior art processing. The problem with this wide gap is for the following layer lithography. It causes poor planarity for this next layer.
In FIG. 4, layer 26 is etched back which tends to increase the planarity of the top surface over closely spaced stripes 20, but does nothing to increase it in the wide gap. In FIG. 5, there is shown a layer 28 deposited by PE/CVD techniques. This layer still does not provide a planar surface over the wide gap. In practice, a second metallurgy layer would be deposited on the surface, after forming via holes to the metal stripes. It is believed apparent that as the metallurgy layers are built up, the surface planarity will deteriorate.
U.S. Pat. No. 5,077,234 proposes a solution to increase planarity of a semiconductor, when the semiconductor contains trenches or the like. The solution proposed utilizes three resist layers, and is believed to be inappropriate to the problem addressed by this invention.